1). Field of the Invention
This invention relates to an electronic assembly and cooling thereof.
2). Discussion of Related Art
Integrated electronic circuits are often formed in semiconductor dies. Such a die is mounted and electrically connected to a package substrate which is then mounted to an electronic substrate such as a motherboard. The package substrate is also electrically connected to the motherboard. Electric signals can be transmitted between metal lines in the motherboard and the electronic circuit so that the electronic circuit is operated.
Operation of the electronic circuit causes heating of the semiconductor die. The electronic circuit may be damaged when the die heats up too much and it may therefore be required to cool the die. The die is typically cooled by mounting a heat sink to the die. Heat can then be transferred from the die to the heat sink and be convected from fins of the heat sink. Alternatively, a fan may be mounted over the die and the fan may blow air onto the die so as to cool the die. A heat sink or a fan increases transfer of heat from a surface of the die opposing the package substrate and the motherboard.
During the manufacture and operation of an electronic assembly that includes an integrated circuit, the die may be subjected to mechanical stresses that can adversely effect any active devices, passive devices, and interconnects that make up the integrated circuit. One example of subjecting the die to stress occurs during bonding, such as flip-chip bonding, of the die to a substrate. The die and substrate are exposed to heat that causes the substrate and die to expand. If the die and the substrate have different coefficients of thermal expansion, then the die and substrate expand at different rates, generating stress on the die. When the die is stressed, any active devices, passive devices, and interconnects formed on the die are also stressed to the point where a mechanical failure can occur in any of the components that make up the die.
One common type of mechanical failure is the shearing of interconnects within the die. Interconnects typically connect devices together in the integrated circuit such that shearing the connections between devices causes catastrophic failure of the integrated circuit.
These types of failures should become even more prevalent in new integrated circuits because next generation processors are likely to include interconnects fabricated from high conductivity materials, such as copper, that are embedded in low strength dielectric materials, such as low-K materials. The low strength dielectric materials in these types of integrated circuits will be highly vulnerable to catastrophic failures such as interconnect shearing.
FIG. 5 is a perspective view of a prior art integrated circuit 1 that includes a die 3 and a guard ring structure 5. Die 3 includes a circuit area 7 and outer edges 9 such that guard ring structure 5 separates outer edges 9 from circuit area 7. Circuit area 7 is located within guard ring structure 5 and is encircled by guard ring structure 5. The guard ring structure 5 on prior art dies 3 does not extend into the area of die 3 that is proximate to outer edges 9. Conventional guard ring structures 5 only relieve mechanical stress in the die 3.
Die 3 is typically fabricated from a semiconductor that has an integrated circuit formed thereon. The integrated circuit 1 typically includes active devices (e.g., diodes and transistors), passive devices (e.g., resistors and capacitors) and interconnects that are formed in circuit area 7. The formation of devices in circuit area 7 includes the formation of devices and interconnects that are diffused, implanted, deposited, or otherwise formed within or above the substrate.
FIG. 6 is a top view of a wafer 8 having at least one prior art die 3 formed thereon. During the manufacture of die 3, wafer 8 is partitioned and sliced into a number of pieces known as dice. Dicing includes slicing wafer 8 along lines 10 that are aligned with outer edges 9 of die 3 to separate die 3 from wafer 8. As wafer 8 is diced, the outer edges 9 of die 3 are mechanically stressed. This stress can create cracks in the outer edges 9 of die 3 that could damage the electronic devices or interconnects on die 3 if the cracks expand into circuit area 7.
Circuit area 7 is fabricated away from outer edges 9 to avoid damage from cracks. In addition, the guard ring structure 5 that encircles circuit area 7 prevents cracks from propagating into circuit area 7. Guard ring structure 5 does not promote heat dissipation.
Therefore, any developments to existing electronic assemblies that (i) increase the ability of electronic assemblies to dissipate thermal energy; and (ii) reduce the potential for damage to integrated circuits caused by cracking due to stress would be desirable.